The present invention relates to circuits for providing voltage reference levels to the ECL (Emitter-Coupled Logic) circuitry of a semiconductor chip.
A typical system for providing a reference voltage level is shown in FIG. 1. A V.sub.bb reference circuit 10 is coupled to a fixed supply voltage, V.sub.cc. A temperature compensation and V.sub.cse reference circuit 12 is also coupled to this V.sub.bb reference circuit. An output driver circuit 14 provides a step down function to the desired voltage level, V.sub.cse and V.sub.bble, as a voltage reference where needed. Elements 10, 12 and 14 form a intermediate voltage reference circuit 16.
Typically, a plurality of voltage reference circuits 16 are arranged around the edges of a semiconductor chip 18 as shown in FIG. 2. Each of these circuits 16 reproduces the reference voltage level for supplying reference levels to designated I/0 (Input/Output) circuits.